| Functions



Formal Arguments and begin-end / fork-join Blocks

SystemVerilog adds the possibility to declare multiple statements in a task or function without requiring a begin...end or fork...join block

function f ;

$display("This is function f");
$display("Function f has no begin-end block");
return 0;

In SystemVerilog functions can have the same formal arguments as tasks (directions: input, output, inout, ref).

If there is no direction in function argument declaration the default direction is input direction. Once a direction is given, subsequent formals default to the same direction.

function reg [3:0] f1(int a,b, output reg [3:0] b,c);
// ...

SystemVerilog allows an array to be specified as a formal argument to a function.

The function with output, inout, or ref arguments cannot be called in an event expression, in an expression within a procedural continuous assignment, or in an expression that is not within a procedural statement. However, a const ref function argument is legal in this context.

Return Values and Void Functions

SystemVerilog introduces void function type. Void function does not have a return value.

function void f2;
$display("This is void function");

Parenthesis are optional in invocations of void functions that accept no arguments.

The nonvoid function can return value by assigning the function name to a value,or by using return statement with a value. The return statement overrides any value assigned to the function name. When the return statement is used, nonvoid functions must specify an expression with the return.

function int f3(input int a,b);
return a+b*3;

Discarding Function Return Values

In SystemVerilog there is possibility to discard a function's return value. Discarding is done by casting the function to the void type:


Constant Function Calls

In SystemVerilog a constant function may call any system function that may be called in a constant expression. This includes $bits and the array query functions. A constant function may reference parameters defined in packages or $unit.

SystemVerilog restrictions on constant functions:

- A constant function cannot not have output, inout, or ref arguments.

- A void function cannot be a constant function.

- An import "DPI" function cannot be a constant function.

- A constant function may have default argument values, but any such default argument value must be a constant expression.


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